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  * qualification standards can be found at www.irf. com ? 2008 international rectifier    august 9, 2011  
       floating channel designed for bootstrap operation  fully operational to + 600 v  tolerant to negative transient voltage, dv/dt immune  gate drive supply range from 10 v to 20 v  undervoltage lockout for both channels  3.3 v and 5 v input logic compatible  matched propagation delay for both channels  logic and power ground +/ 5 v offset  lower di/dt gate driver for better noise immunity  output source/sink current capability 1.4 a/1.8 a  lead free, rohs compliant  
 topology halfbridge v offset 600 v v out 10 v C 20 v i o+ & i o (typical) 1.9 a & 2.3 a t on & t off (typical) 680 ns & 270 ns deadtime (typical) 400 ns (r dt = 0 ) 5 s (r dt = 200 k)
 !"#$% &#$'(%%$%               mlpq4x4 16 leads (without 2 leads)  downloaded from: http:///
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    $#$%  the IRS21844Mpbf is a high voltage, high speed power mo sfet and igbt drivers with dependent high and lowside referenced output channels. proprietary h vic and latch immune cmos technologies enable ruggedized monolithic construction. the logic input i s compatible with standard cmos or lsttl output, down to 3.3 v logic. the output drivers feature a high pul se current buffer stage designed for minimum driver crossconduction. the floating channel can be used to drive an nchannel power mosfet or igbt in the highside configuration which operates up to 600 v.   (#$%)*+,-*+,*+    .'$/$$%%/$% ?  industrial ?? (per jedec jesd 47) .'$/$$%0' comments: this ic has passed jedecs industrial qualification. irs consumer qualification level is granted by extension of the higher industrial level. $%$$0$0'  mlpq4x4 14l msl2 ??? (per ipc/jedec jstd020) machine model class a (+/100v) (per jedec standard jesd22a115) human body model class 1c (+/1500v) (per eia/jedec standard eia/jesd22a114)   charged device model class iii (+/1000v) (per jedec standard jesd22c101) (12#&  class ii, level a (per jesd78a)  (#'$% yes  ? qualification standards can be found at international rectifier s web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such requirements. please contact your international rectifier sales representative for f urther information. ??? higher msl ratings may be available for the specific p ackage types listed here. please contact your international rectifier sales representative for further infor mation.   part input logic cross conduction prevention logic deadtime ground pins ton/toff 2181 com 21814 hin/lin no none v ss /com 180/220 ns 2183 internal 500ns com 21834 hin/lin yes programmable 0.4 C 5 us v ss /com 180/220 ns 2184 internal 500ns com 21844 in/sd yes programmable 0.4 C 5 us v ss /com 680/270 ns downloaded from: http:///
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  %"#$%!(%$$% the input/output logic timing diagram is shown in figur e 1. for proper operation the device should be used within the recommended conditions. the v s and v ss offset rating are tested with all supplies biased at a 1 5 v differential. ?? logic operational for v s of 5 v to +600 v. logic state held for v s of 5 v to Cv bs . (please refer to design tip dt973 for more details). ??? hin and lin are internally clamped with a 5.2 v zener diode.  3' 4$$%!   absolute maximum ratings indica te sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air condit ions. 3' /$%$$% $% 4 2%$ v b highside floating absolute voltage 0.3 620 v s highside floating supply offset voltage v b 25 v b + 0.3 v ho highside floating output voltage v s 0.3 v b + 0.3 v cc lowside and logic fixed supply voltage 0.3 20 ? v lo lowside output voltage 0.3 v cc + 0.3 dt programmable deadtime pin voltage v ss 0.3 v cc + 0.3 v in logic input voltage ( in & sd ) v ss 0.3 v cc + 0.3 v ss logic ground v cc 20 v cc + 0.3 v dv s /dt allowable offset supply voltage transient 50 v/ns p d package power dissipation @ ta 25c 2.08 w rth ja thermal resistance, junction to ambient 36 c/w t j junction temperature 150 t s storage temperature 50 150 t l lead temperature (soldering, 10 seconds) 300 c ? all supplies are fully tested at 25 v and an internal 20 v c lamp exists for each supply. 3'  /$%$$% $% 4 2%$ v b highside floating supply absolute voltage v s + 10 v s + 20 v s highside floating supply offset voltage (??) 600 v ho highside floating output voltage v s v b v cc lowside and logic fixed supply voltage 10 20 v lo lowside output voltage 0 v cc v in logic input voltage ( in & sd ) ( ???) v ss v cc dt programmable deadtime pin voltage v ss v cc v ss logic ground 5 5 v t a  ambient temperature 40 125 c  downloaded from: http:///
    www.irf.com ? 2008 international rectifier  
  %$'$'(1$$ v bias (v cc , v bs ) = 15 v, v ss = com, c l = 1000 pf, t a = 25  c, dt = v ss unless otherwise specified. 3' /$%$$% $%  &#   4  2%$  &(%$$% t on turnon propagation delay 680 900 v s = 0 v t off turnoff propagation delay 270 400 v s = 0 v or 600 v t sd shutdown propagation delay 180 270 mt on delay matching, hs & ls turnon 0 90 mt off delay matching , hs & ls turnoff 0 40 t r turnon rise time 40 60 t f turnoff fall time 20 35 v s = 0 v 280 400 520 ns r dt = 0 dt deadtime: lo turnoff to ho turnon (dt loho ) & ho turnoff to lo turnon (dt holo ) 4 5 6 s r dt = 200 k 0 50 r dt = 0 mdt deadtime matching dt loho dt holo 0 600 ns r dt = 200 k $'$'(1$$ v bias (v cc , v bs ) = 15 v, v ss = com, dt = v ss and t a = 25  c unless otherwise specified. the v il, v ih and i in parameters are referenced to v ss /com and are applicable to the respective input leads: in and sd . the v o, i o and r on parameters are referenced to com and are applicable to the r espective output leads: ho and lo.  3' /$%$$% $%  &#   4  2%$  &(%$$% v ih logic 1 input voltage for ho & logic 0 for lo 2.5 v il logic 0 input voltage for ho & logic 1 for lo 0.8 v sd,th+ sd input positive going threshold 2.5 v sd,th sd input negative going threshold 0.8 v cc = 10 v to 20 v  v oh high level output voltage, v bias v o 1.4 i o = 0 a v ol low level output voltage, v o 0.2 v  i o = 20 ma i lk offset supply leakage current 50 v b = v s = 600 v i qbs quiescent v bs supply current 20 60 150 a i qcc quiescent v cc supply current 0.4 1.0 1.6 ma v in = 0 v or 5 v i in+ logic 1 input bias current 25 60 in = 5 v, sd = 0 v i in logic 0 input bias current 5.0 a in = 0 v, sd = 5 v v ccuv+ v bsuv+ v cc and v bs supply undervoltage positive going threshold 8.0 8.9 9.8 v ccuv v bsuv v cc and v bs supply undervoltage negative going threshold 7.4 8.2 9.0 v ccuvh v bsuvh hysteresis 0.3 0.7 v i o+ output high short circuit pulsed current 1.4 1.9 v o = 0 v, pw 10 s i o output low short circuit pulsed current 1.8 2.3 a v o = 15 v, pw 10 s downloaded from: http:///
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6 3'  $#$% 1 sd logic input for shutdown (referenced to v ss ) 2 v ss logic ground 3 dt programmable deadtime lead, referenced to v ss 4 com lowside return 5 lo lowside gate drive output 6 nc no connection 7 v cc lowside and logic fixed supply 8 nc no connection 9 nc no connection 10 nc no connection (removed lead) 11 v s highside floating supply return 12 ho highside gate drive output 13 v b highside floating supply 14 nc no connection 15 nc no connection (removed lead) 16 in logic input for highside gate driver output (ho), in phase   $!%%)  
16l mlpq 4x 4 with 2 leads removed = removed lead 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16   dt ("  " nc nc 
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  ##'$$%%/$%%$$%'$' sd $!)%#,"#&$$%!$!   $!)7$1$%!&$80//$%$$ %  sd $!-)17%80//$%$$%  $!)$80//$%$$%  50% 10% 90% mt lo ho 50% ho mt lo in (lo) in (ho) $!9)' 1$%!80//$%$$%  downloaded from: http:///
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63 tube/bulk 92 IRS21844Mpbf irs21844 mlpq 4x416l  
 IRS21844Mtrpbf    the information provided in this document is believ ed to be accurate and reliable. however, internation al rectifier assumes no responsibility for the consequences of the use of t his information. international rectifier assumes n o responsibility for any infringement of patents or of other rights of third parties which may result from the use of this info rmation. no license is granted by implication or otherwise under any patent or patent rights of international rectifier. the specificat ions mentioned in this document are subject to change without notice. this document su persedes and replaces all information previously su pplied. for technical support, please contact irs technical assistance center http://www.irf.com/technicalinfo/ 8" .2&) 233 kansas st., el segundo, california 90245 tel: (310) 2527105  downloaded from: http:///


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